1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a test device for testing a test-object circuit.
2. Description of the Related Art
Semiconductor devices such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) need to be tested in various ways before being put on the market. Such circuits may be tested on a Field Programmable Gate Array (FPGA). A FPGA is advantageous because it is capable of being quickly designed, has low implementation cost, and has design flexibility. Therefore, it is frequently used for testing integrated circuits. However, it is difficult to test fully customized circuits, designed from a transistor level, on an FPGA.
The process of designing the test-object circuit and synthesizing the test-object circuit on the FPGA will be described.
After the test-object circuit is designed through a schematic tool, the schematic tool generates a netlist corresponding to the test-object circuit. A netlist is a file generated by a schematic tool for simulation or for Layout Versus Schematic (LVS) automation. The netlist contains information on the synthesized circuit including interconnection relationships and nodes of the synthesized circuit, which are identifiable using the FPGA. The FPGA applies the netlist and performs test operations on the synthesized circuit. However, in custom-designed circuits that have a lot of asynchronous elements, logic simulation may be performed but it is difficult to evaluate such a circuit on an FPGA.